This paper studies how to do fault‑tolerant quantum operations when a computer is built from separate modules. Each module is a quantum processing unit (QPU). The modules are linked by shared entanglement called Bell pairs. The authors ask whether errors on those links make it impossible to perform the logical gates needed for large quantum computations.

To answer this, the team simulated logical CNOT gates between modules using lattice surgery. Lattice surgery is a way to make entangling logical gates by measuring patterns of the underlying error‑correcting code rather than by applying the same physical gate across all qubits. The code they use is the rotated surface code, a widely studied quantum‑error‑correcting code. Cross‑module steps that need two‑qubit interactions are implemented by gate teleportation that uses noisy Bell pairs. The authors model noise at the circuit level with depolarizing errors applied after single‑ and two‑qubit gates, and they give nonlocal (cross‑module) two‑qubit gates an extra error factor α. Simulations ran 50,000 trials per data point and used the software LOOM and STIM for circuits and PyMatching for decoding.

The main numerical finding is that distributed implementations remain close in performance to monolithic ones. Allowing cross‑module gates to be noisier by about an order of magnitude still gives only a small drop in the fault‑tolerance threshold. In the cases studied, the gap between distributed and monolithic thresholds was about 2×10−3 to 3×10−3 in physical error rate. The authors report that the threshold behavior is dominated by local, inside‑module gate noise rather than the extra noise on the interfaces. This suggests modular architectures can scale even when links are noticeably noisier than the modules themselves.

The paper also addresses preparing distributed logical GHZ states, which are multi‑party entangled states useful in experiments and protocols. The authors design a protocol that reduces the number of ancilla logical qubits, the time to prepare the state, and the number of nonlocal Bell pairs consumed. They show that minimizing ancilla use maps to a vertex‑cover problem on a graph representing the QPU network, and they present a polynomial‑time heuristic to find low‑overhead solutions.