Quantum processors can prepare clustered non‑Abelian fractional quantum Hall states using fixed‑depth circuits
This paper shows that certain exotic quantum states, known as clustered non‑Abelian fractional quantum Hall (FQH) states, can be prepared on programmable quantum processors with a circuit cost that does not grow with system size. Fractional quantum Hall matter supports quasiparticles with unusual fractional charge and, in some cases, non‑Abelian exchange statistics — a property that makes them interesting for fundamental physics and potential quantum technology. The authors find that the more exotic clustered states are actually cheaper to make on digital hardware than the more common Laughlin states.
The team developed a systematic pipeline that starts from a family’s defining ‘‘pattern of zeros’’ and builds a positive semidefinite parent Hamiltonian (a mathematical operator whose ground state is the target wavefunction). From that they derive local circuit recipes, translate them into device gates, and run them on an IBM Heron quantum processor with a heavy‑hex qubit layout. Using this approach they prepared and checked 18 different FQH families across the full 156‑qubit device. Notable demonstrations include a parafermionic Read–Rezayi Z3 state kept at two‑qubit gate depth three for systems from 8 to 118 qubits, and ‘‘full root’’ sampling for a Read–Rezayi Z4 state on 154 qubits with 104 electrons. Other families prepared include Moore–Read, Gaffnian and Haffnian ladders.
At a high level the difference in cost comes from how particles are allowed to cluster in the target state. The authors show a clear ‘‘clustering dichotomy.’’ Clustered states allow squeezing operations that act on disjoint groups of particles. Those operations can run in parallel, so the required two‑qubit depth stays constant as the system grows. By contrast, the Laughlin family forces squeezes that share particles; the corresponding gates must be applied in sequence, so two‑qubit depth grows roughly linearly with system size. Circuit depth here means how many layers of two‑qubit gates must be applied one after another; fewer layers generally make circuits easier to run accurately on real hardware.